AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

VeeR EH1 core

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

Test suite designed to check compliance with the SystemVerilog standard.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

VeeR EL2 Core

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Virtio implementation in SystemVerilog

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

Basic Common Modules

NTUEE Digital Circuit Lab 24Fall

RISCV core RV32I/E.4 threads in a ring architecture

High quality and composable RTL libraries in SystemVerilog

Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.

Register-based and RAM-based FIFOs designed in Verilog/System Verilog.

APB master and slave developed in RTL.

Generate verilog register file from systemRDL description

Common SystemVerilog RTL modules for RgGen

Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numerical sauce. The best of all is that the sauce is not secret, but fully open to the public.