比做算法的懂工程落地，比做工程的懂算法模型。

ASIC implementation flow infrastructure

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

Parametric layout generator for digital, analog and mixed-signal integrated circuits

Skywater 130nm Klayout Device Generators PDK

Submission template for Tiny Tapeout IHP shuttles - Verilog HDL Projects

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah

Open NPU is an open-source project dedicated to creating a flexible, extensible, and high-performance neural processing unit (NPU) architecture. Open NPU aims to democratize access to cutting-edge neural processing technology for machine learning and AI applications.

Conda + KLayout

Hack4Her: Logic Synthesis for AI

xspcomm encapsulates the DPI-based digital circuit and provides various high-level language operation interfaces.

This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.

GDSII/OASIS layouts, including fractals, generated in working Google Colab notebooks. Layout previews are plotted as 2D graphics before exporting.

Carleton University / ELEC4609 Integrated Circuit Design and Fabrication / Project: Static Logic PRSG (Pseudo Random Sequence Generator) chip design, fabrication and testing.

VHDL Projects that I've created during the course Programmable Logic Devices in West Pomeranian University of Technology in Szczecin.

A curated list of surveys, reviews, and awesome lists on the application of Large Language Models (LLMs) and AI for Electronic Design Automation (EDA) and chip design.

build custom asics and fpga's using llms.

Final Project for Digital Integrated Circuits. SoupVenture Chip.

This repository contains the report of the Week 2 task for VSD RV SoC Tapeout Program