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Machine learning on FPGAs using HLS

Send video/audio over HDMI on an FPGA

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Documenting the Xilinx 7-series bit-stream format.

An abstraction library for interfacing EDA tools

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

Installs Vivado on M1/M2/M3 macs

Notes on the Red Pitaya Open Source Instrument

HDL support for VS Code

Build Customized FPGA Implementations for Vivado

FPGA Accelerator for CNN using Vivado HLS

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Image Processing Toolbox in Verilog using Basys3 FPGA

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

基于 pcileech-fpga 的自定义/修改 DMA固件创建的详细说明

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

车牌识别,FPGA,2019全国大学生集成电路创新创业大赛

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.