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rv32imc

Here are 4 public repositories matching this topic...

syntacore / scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core riscv rtl ip verilog risc-v rv32i rv32e rv32imc rv32emc

Updated Sep 26, 2024
SystemVerilog

tekno-kizil

KASIRGA-KIZIL / tekno-kizil

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

asic cpu fpga processor llvm verification clang riscv rtl verilog computer-architecture pipeline-processor in-order risc-v coremark rv32imc teknofest openlane

Updated Jul 20, 2023
Verilog

rob-ng15 / Silice-Playground

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

fpga forth risc-v rv32i j1-cpu de10nano rv32 rv32im rv32imc ulx3s fomu

Updated Jul 2, 2023
C

djzenma / RV32IC-CPU

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

cpu verilog risc hdl pipeline-processor verilog-hdl risc-v rv32i verilog-snippets pipeline-cpu risc-processor riscv32 riscv-simulator rv32imc verilog-code riscv32im

Updated May 29, 2020
Verilog

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