openlane
Here are 35 public repositories matching this topic...
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
-
Updated
Mar 26, 2022 - Verilog
Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
-
Updated
Oct 14, 2024 - Python
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
-
Updated
Sep 17, 2022
Gate-level visualization generator for SKY130-based chip designs.
-
Updated
Jul 22, 2021 - Python
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
-
Updated
Jul 7, 2021
Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah
-
Updated
Oct 19, 2024
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
-
Updated
Jul 19, 2022 - Verilog
CLEAR is an Open Source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC design tools used to create it.
-
Updated
Mar 19, 2022 - Verilog
This is part of EC383 - Mini Project in VLSI Design.
-
Updated
May 8, 2022 - Verilog
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
-
Updated
Jan 23, 2024 - Verilog
Report of the contents learned in the 5-day workshop by VSD regarding the open-source EDA tools in the VLSI industry
-
Updated
Feb 25, 2021
Improve this page
Add a description, image, and links to the openlane topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the openlane topic, visit your repo's landing page and select "manage topics."