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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

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  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4k 597

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.3k 1.1k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.4k 214

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1k 329

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 818 221

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 729 177

Repositories

Showing 10 of 109 repositories
  • Surelog Public

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/Surelog’s past year of commit activity
    C++ 363 Apache-2.0 69 51 (2 issues need help) 0 Updated Nov 10, 2024
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 94 Apache-2.0 44 100 58 Updated Nov 10, 2024
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 119 Apache-2.0 23 16 23 Updated Nov 10, 2024
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 5 1 0 0 Updated Nov 10, 2024
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 75 Apache-2.0 37 67 10 Updated Nov 9, 2024
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 3,984 Apache-2.0 597 313 (1 issue needs help) 168 Updated Nov 9, 2024
  • firrtl-spec Public

    The specification for the FIRRTL language

    chipsalliance/firrtl-spec’s past year of commit activity
    TeX 45 28 22 17 Updated Nov 9, 2024
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 295 ISC 75 45 (5 issues need help) 21 Updated Nov 8, 2024
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 252 Apache-2.0 75 24 10 Updated Nov 8, 2024
  • tac Public

    CHIPS Alliance Technical Advisory Council

    chipsalliance/tac’s past year of commit activity
    6 Apache-2.0 22 20 2 Updated Nov 8, 2024
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