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Weiyet/README.md

Hi there ๐Ÿ‘‹ Wei Yet Here

Just a lazy noobie here. Expert and enthusiast of nothing, striving to be a "Full Stack" Engineer! JUST FOR FUN! Identify, learn, and solve.

Hardware Skill

  • Verilog, SystemVerilog, VHDL, Python, Tcl, Perl, Linux, Makefile, Bash scripting
  • ASIC/FPGA RTL design and verification (UVM, Formal, SVA, cocoTB), Arduino, Rashpberry Pi
  • Microcontroller subsystem, digital subsystem for mixed-signal block, computer architecture
  • Vivado, Modelsim, Cadence, Synopsys, Open-Source EDA (Icarus Verilog, Yosys)
  • (EXPLORING NOW --> Networking interface, FPGA, cocoTB + PyUVM, and MORE)

Software Skill

  • NA ๐Ÿ˜ญ๐Ÿ˜ž When can I be smart and hardworking enough to learn software skills, too? Can somebody teach me, especially low-level, high-performance stuff? C++ guys are so cool!

LinkedIn

Popular repositories Loading

  1. RTLStructLib RTLStructLib Public

    RTL data structure

    SystemVerilog 47 2

  2. LF-Building-a-RISC-V-CPU-Core LF-Building-a-RISC-V-CPU-Core Public

    Forked from stevehoover/LF-Building-a-RISC-V-CPU-Core

    LinuxFoundationX: Building a RISC-V CPU Core

    TL-Verilog 1

  3. Arduino_Console Arduino_Console Public

    C++ 1

  4. Maze_Solver_RTL Maze_Solver_RTL Public

    Python 1

  5. Weiyet Weiyet Public