AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

VeeR EH1 core

这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS

AMBA AXI VIP

VeeR EL2 Core

Network on Chip Implementation written in SytemVerilog

An FPGA-based AXI4 DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

An AXI4 crossbar implementation in SystemVerilog

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

AXI4 and AXI4-Lite interface definitions

SDRAM controller with AXI4 interface

Minimal DVI / HDMI Framebuffer

UART -> AXI Bridge

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

SPI-Flash XIP Interface (Verilog)

HLS for Networks-on-Chip

Quasar 2.0: Chisel equivalent of SweRV-EL2