AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Aug 27, 2026 - SystemVerilog
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axi4
Here are 105 public repositories matching this topic...
VeeR EH1 core
fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer
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Jul 16, 2026 - SystemVerilog
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2
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Sep 2, 2026 - SystemVerilog
Network on Chip Implementation written in SytemVerilog
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Aug 27, 2022 - SystemVerilog
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
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Nov 18, 2024 - SystemVerilog
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
simulation vhdl verification vip tlm testbench osvvm simulation-modeling axi4 axi4-lite axi4-stream verification-component
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Sep 2, 2026 - VHDL
AXI4 and AXI4-Lite interface definitions
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Sep 20, 2020 - SystemVerilog
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
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Jun 6, 2020 - C++
Minimal DVI / HDMI Framebuffer
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Aug 9, 2020 - Verilog
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
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Dec 6, 2023 - VHDL
HLS for Networks-on-Chip
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Feb 18, 2021 - C++
RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.
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Mar 13, 2025 - Verilog
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