Verilator open-source SystemVerilog simulator and lint system
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Aug 4, 2026 - SystemVerilog
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system-verilog
Here are 149 public repositories matching this topic...
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design
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Feb 2, 2026 - SystemVerilog
Control and Status Register map generator for HDL projects
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May 24, 2025 - Python
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
simulator encoder decoder priority verilog xilinx testbenches multiplexer comparator adder system-verilog xilinx-vivado half-adder traffic-light-controller full-adder ripple-adder look-ahead-adder
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Oct 2, 2019 - Verilog
RTL data structure
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Apr 23, 2026 - SystemVerilog
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
fsm mips tcl labs verilog alu hse modelsim system-verilog mips-architecture quartus-prime quartus miem terasic-de10-lite terasic verilog-designs ddlm schoolmips dmk-press verilog-book
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Sep 15, 2023 - Verilog
ICRTL Benchmark: Industrial-level RTL design challenges for evaluating PPA optimization, code generation, and LLM applications in EDA.
benchmark evolution natural-language ppa eda rtl verilog system-verilog yosys ic-design vlsi-design rtl-design hardware-accelerator ai-agent verilogeval rtllm llm-benchmark spec-to-rtl
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Jul 3, 2026 - SystemVerilog
Connecting FPGA and Arduino using SPI.
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Apr 30, 2022 - Verilog
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
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Jun 5, 2023 - SystemVerilog
A prototype of Concolic Testing engine for SystemVerilog, developed as part of PFN summer internship 2018.
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Dec 21, 2018 - OCaml
Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
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Mar 13, 2024 - SystemVerilog
Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types).
fpga vivado computer-architecture system-verilog risc-v cpu-architecture processor-design single-cycle-processor digital-design-and-computer-organization rv32i-processor
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Jul 21, 2025 - SystemVerilog
This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.
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Aug 3, 2026 - SystemVerilog
My solutions for Bilkent University CS224 Computer Organization Labs (Spring 2019). Includes assembly programming assignments together with various processor designs in System Verilog HDL
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Jun 10, 2019 - Assembly
AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
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Mar 22, 2017 - SystemVerilog
openENOC is an open-source Ethernet-based NoC for scalable MPSoC systems, using Layer-2 frame switching to connect CPUs, accelerators and peripherals for crypto, AI and edge computing.
acceleration networking fpga riscv rtl ethernet soc system-verilog risc-v mpsoc noc network-on-chip gateware
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Jul 25, 2026 - Python
Example of Python and PyTest powered workflow for a HDL simulation
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Jan 17, 2021 - Python
Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog
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Jun 3, 2024 - Verilog
16 bit serial multiplier in SystemVerilog
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Oct 13, 2018 - SystemVerilog
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