Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.

This repository contains VHDL implementations for all hardware design challenges (quests/questions) featured on the chipdev.io website.

A VHDL code base that contains Utility Packages for both HDL and Testbenches

Fully functional RISC-V compatible multicycle CPU built in Verilog. Includes ALU, datapath, FSM controller, memory, and testbenches.

8-bit CPU in Verilog - implements fetch-decode-execute cycle with custom ISA, simulated using Icarus Verilog

Synchronous FIFO implementation in Verilog with testbench and simulation waveforms

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

5-stage MIPS pipeline CPU in Verilog with data forwarding, hazard detection and full instruction set. Simulated on EDA Playground.

UART Transmitter/Receiver in Verilog - 9600 baud, 8-bit, full loopback tested. Simulated on EDA Playground with Icarus Verilog.

Verilog HDL implementation of a 5-stage pipelined RISC-V processor with Hazard Detection and Forwarding Unit verified using EDA playground and EPWave.

Implementation of 4-bit Arithmetic Logic Unit using structural modeling in Verilog. Features 8 operations controlled by 3-bit select line. Simulated on EDA Playground with waveform analysis.

SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

UVM extension for JSON transaction recording and waveform visualization — runs on EDA Playground or locally