An open-source collection of embedded development and debugging skills for Claude Code, Copilot, TRAE, and other AI coding assistants that support the Skill protocol. Once installed, the AI assistant can directly operate compilers, debuggers, and communication buses, automating the full workflow from code generation to hardware verification.

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

A Platform for High-Level Parametric Hardware Specification and its Modular Verification

Welcome to the ultimate list of resources for formal verification techniques and tools. This repository aims to provide an organized collection of high-quality resources to help professionals, researchers, and enthusiasts stay updated and advance their knowledge in the field.

CoreIR Symbolic Analyzer

This repo is created to include illustrative examples on object oriented design pattern in SV

A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.

The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.

8-bit combinational ALU built from scratch with 3,488 CMOS transistors (KiCad + SPICE + Logisim + 1.24M tests

Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.

VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (RL). It provides a generic Gym environment implementation for building cocotb-based testbenches for verifying any hardware design.

Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators

Deterministic structural sanity checker for Verilog RTL — undriven outputs, multi-driven signals, latch-inference risks, blocking/nonblocking misuse. Pure Python stdlib.

Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification

Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT

Expose what functional RTL benchmarks leave unanswered. Evidence profiles for AI-generated RTL; research collaborators and design partners welcome. Alpha research software, seeking validation

An experimental HDL simulator written in Common Lisp focused on interactive and extensible hardware design and verification.

A Coq framework to support structural design and proof of hardware cache-coherence protocols

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

Btor2 parser, circuit mitter, and code optimizer