AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
Methylation array preprocessing.
A collection of formal properties for hardware buses, and cores using them.
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
Example of hardware trojan in a router detected with formal property verification
A repo for small SVA examples
A short paper I wrote about John Deere and their SVA metric in Europe
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