Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
AI-assisted RFIC optimization framework combining ONNX surrogate models, Qucs-S/Xyce circuit simulation, and AWS Palace fine-tuning for open-source electronic design automation (EDA).
Traceable datasheet-to-SPICE model generation for power MOSFETs and diodes, with browser extraction and validation benchmarks.
Agentic, evidence-driven Spec-to-RTL-to-GDS workflow with verified RTL and managed LibreLane implementation
SHA-256 accelerator on Caravel SoC (SkyWater 130nm) - open-source RTL-to-GDSII signoff flow
Open-source MBIST generator for OpenRAM SRAM macros with BIRA/BISR redundancy repair (row + column, tester-driven and autonomous on-chip), a shared-bus multi-memory controller, and a programmable march-algorithm fault-model research platform.
A curated list of semiconductor industry resources, with a deliberate bias toward sub-10nm logic, lithography, process technology, and advanced packaging.
Open-source, modular simulator for optical communication links and photonic systems. Design phase — architecture under review.
4-bit ALU RTL to Gate-Level Synthesis using Yosys + ABC on EDA Playground
Open research toward model-specific mask-ROM LLM inference silicon: analytical studies, an ABI 3.0 compiler/runtime and cycle model, synthesizable RTL, and open-PDK physical evidence — gated against itself by a 19-rung board that is deliberately mostly red.
A free UVM course that runs end to end on Verilator — no EDA licences. 8 units over 7 days (plus an optional day 8), 444 slides, 38 runnable examples with functional coverage, 19 exercises and an APB capstone. In English and Spanish, CC BY 4.0.
Open-source compiler for C⏚ - a C-like hardware language that compiles to clean, standard Verilog or VHDL.
Tiny Tapeout TTSKY26c (sky130A): on-chip metastability characterizer -- ring-osc async data + 41-tap delay line + dual-sample witness FFs; raw UART stream for tau/W and MTBF extraction
Synthesis-script search on open-source EDA (yosys + berkeley-abc), where every candidate must be proven equivalent before its area or depth is allowed to mean anything.
Block-RAM memory subsystem through the open-source iCE40 flow (Yosys, nextpnr, icetime, icepack) on two devices, with the same tests passing on RTL and on the mapped netlist.
Model Context Protocol server for Yosys RTL synthesis, cell statistics, and latch triage
A decode-phase KV-cache engine for LLM inference: SystemVerilog RTL to a sign-off-clean GDSII on SkyWater 130nm (0 DRC, 0 LVS, timing closed), with a formally proved paged allocator and a 16-node sequence-parallel mesh over a torus NoC.
Research portfolio on analog layout techniques, structure-aware generation, B*-tree placement, well-domain repair, and access-aware routing.
Landing page for AI agent tooling for hardware + ML systems (MCP, skills, EDA containers)
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