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rtl-engineering

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panktipatel1711 / Low-Power-ALU-Arithmetic-Logic-Unit-Design-using-Verilog

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A parameterized (8/16/32-bit) Low-Power ALU in Verilog featuring structural Operand Isolation and register-level Clock Gating to minimize dynamic power dissipation ($P_{dynamic}$). Simulation-ready for EDA Playground and Icarus Verilog.

verilog computer-architecture alu icarus-verilog digital-design hardware-description-language eda-playground low-power-vlsi rtl-engineering asic-architecture
  • Updated Jun 22, 2026
  • Verilog

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