A hardware-verified 8-bit Synchronous FIFO implemented on Xilinx Spartan-6 FPGA using Verilog HDL. Features robust signal debouncing, power-on reset logic, and real-time status monitoring.
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Updated
Apr 15, 2026 - SystemVerilog
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synchronous-fifo
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RTL Design and Verification of a Parameterized Synchronous FIFO in Verilog with directed, corner, and randomized test cases.
lint verilog gtkwave fifo vlsi yosys iverilog icarus verilator hardware-design rtl-design-and-verification rtl-design-and-simulation synchronous-fifo
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Jul 4, 2026 - Verilog
A hardware-verified 8-bit Synchronous FIFO implemented on Xilinx Spartan-6 FPGA using Verilog HDL. Features robust signal debouncing, power-on reset logic, and real-time status monitoring.
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Updated
May 16, 2026 - SystemVerilog
RTL implementation of a parameterized synchronous FIFO in Verilog HDL with read/write operations, full and empty flag generation, overflow and underflow detection, and comprehensive testbench simulation using ModelSim.
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Jul 10, 2026 - Verilog
Synchronous FIFO implementation in Verilog with testbench and simulation waveforms
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May 21, 2026 - Verilog
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