Commits

Commits on Aug 26, 2024

[FreezePaths] Add an optional argument, to get the operation name (#7549 )
prithayan
committedAug 26, 2024

Commits on Aug 12, 2024

[CreateSifiveMetadata] Update memory hierarchy paths to be pre-extrction (#7491 )
prithayan
committedAug 12, 2024

Commits on Jul 19, 2024

[Seq] Canonicalize firreg with a preset (#7350 )
prithayan
committedJul 19, 2024

Commits on Jul 9, 2024

[HW] Specify llvm::SmallVector namespace. NFC. (#7293 )
prithayan
committedJul 9, 2024

Commits on Jun 18, 2024

[HW] Move the CombDataFlow op interface from FIRRTL to HW (#7195 )
prithayan
committedJun 18, 2024

Commits on Jun 13, 2024

[FIRRTL] Add a new op interface for combinational loop detection. (#7120 )
prithayan
committedJun 13, 2024

Commits on Jun 11, 2024

[FIRRTL][CreateSiFiveMetadata] Add the path to the DUT, in the SiFive metadata class (#7156 )
prithayan
committedJun 11, 2024

Commits on May 23, 2024

[LowerClasses] Ensure classes are instantiated by an object. (#7072 )
prithayan
committedMay 23, 2024

Commits on May 16, 2024

[CreateSifiveMetadata] Fix a typo in the field name (#7046 )
prithayan
committedMay 16, 2024

Commits on May 10, 2024

[AddSeqMemPorts] Add hierpathop to verbatim, instead of raw instance path (#7014 )
prithayan
committedMay 10, 2024

Commits on Apr 11, 2024

[LowerFirReg] Reimplement the mux reachability analysis (#6914 )
prithayan
committedApr 11, 2024

Commits on Apr 9, 2024

Revert "[LowerFirReg] Reimplement the mux reachability analysis (#6709 )"
prithayan
committedApr 9, 2024
[LowerFirReg] Reimplement the mux reachability analysis (#6709 )
prithayan
committedApr 9, 2024

Commits on Apr 8, 2024

[CreateSiFiveMetadata] Generate firrtl.class instead of om.class (#6736 )
prithayan
committedApr 8, 2024

Commits on Mar 16, 2024

[InferReadWrite] Set builder insertion point to ensure dominance (#6836 )
prithayan
committedMar 16, 2024

Commits on Mar 14, 2024

[InferReadWrite] Add heuristic to infer unmasked memory (#6790 )
prithayan
committedMar 14, 2024
[InferRW] Remove dependence of write-mode on enable for memory (#6818 )
prithayan
committedMar 14, 2024

Commits on Mar 4, 2024

LLVM bump (#6782 )
prithayan
committedMar 4, 2024

Commits on Jan 19, 2024

[CheckCombLoops] Refactor comb loop detection pass (#5647 )
prithayan
committedJan 19, 2024

Commits on Dec 22, 2023

[ModuleInliner] Donot retop if flattening the module (#6515 )
prithayan
committedDec 22, 2023

Commits on Dec 18, 2023

[LowerToHW] Fix output port index mapping (#6530 )
prithayan
committedDec 18, 2023

Commits on Dec 7, 2023

[FlattenIO] Fix module input and output port name order. (#6495 )
prithayan
committedDec 7, 2023

Commits on Dec 1, 2023

[FIRRTL][NFC] Add clockgate instName to FirtoolOptions setters. (#6460 )
prithayan
committedDec 1, 2023

Commits on Nov 28, 2023

[HW][FlattenIO] Fix extern module instances (#6441 )
prithayan
committedNov 28, 2023

Commits on Nov 17, 2023

[FIRRTL][LowerType] Handle unrealized_conversion_cast of other dialects (#6422 )
prithayan
committedNov 17, 2023

Commits on Oct 26, 2023

[FIRRTL] Add argument to detect flipped fields with walkGroundTypes (#6344 )
prithayan
committedOct 26, 2023
[FIRRTL] Add a new pass to detect ops that will fail simulation (#6341 )
prithayan
committedOct 26, 2023

Commits on Oct 12, 2023

[ExtractTestCode] Use non-empty unqiue port names (#6283 )

prithayan
and
nandor
committedOct 12, 2023

Commits on Oct 10, 2023

[OM] Add location info to EvaluatorValue (#6240 )
prithayan
committedOct 10, 2023

Commits on Sep 27, 2023

Commits on Sep 20, 2023

[ExportVerilog] Add verilog debug locations to output MLIR (#6092 )
prithayan
committedSep 20, 2023

Commits on Sep 19, 2023

[OM] Python bindings for om integer (#6042 )
prithayan
committedSep 19, 2023

Commits on Sep 14, 2023

[OM] Add path append op (#6073 )
prithayan
committedSep 14, 2023