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[ModuleInliner] Donot retop if flattening the module (#6515)
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If a `HierPathOp` has a root module that is flattened and inlined, then donot
 retop the root module, this results in incorrect `HierPathOp` that as stale
 symbols. 
This commit fixes the issue.
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prithayan authored Dec 22, 2023
1 parent ae417df commit 81543a1
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Showing 2 changed files with 30 additions and 1 deletion.
2 changes: 1 addition & 1 deletion lib/Dialect/FIRRTL/Transforms/ModuleInliner.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1150,7 +1150,7 @@ void Inliner::inlineInstances(FModuleOp module) {
// participate in any HierPathOp. But the reTop might add a symbol to it, if
// a HierPathOp is added to this Op.
DenseMap<Attribute, Attribute> symbolRenames;
if (!rootMap[target.getNameAttr()].empty()) {
if (!rootMap[target.getNameAttr()].empty() && !toBeFlattened) {
for (auto sym : rootMap[target.getNameAttr()]) {
auto &mnla = nlaMap[sym];
sym = mnla.reTop(module);
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29 changes: 29 additions & 0 deletions test/Dialect/FIRRTL/inliner.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -1417,3 +1417,32 @@ firrtl.circuit "PropertyUTurn" {
}
firrtl.extmodule @Consume(in in : !firrtl.string)
}

// -----

// Test that inlining and flattening compose with nla well.
firrtl.circuit "compose_nla" {
hw.hierpath private @nla1 [@test1::@sym, @test2::@sym, @test3]
// CHECK-NOT: hw.hierpath private @nla1
firrtl.module @compose_nla() {
// CHECK-LABEL: firrtl.module @compose_nla() {
firrtl.instance test1 @test1()
firrtl.instance test2 @test2()
firrtl.instance test3 @test3()
}
firrtl.module private @test1() attributes {annotations =
[{class = "firrtl.transforms.FlattenAnnotation"},
{class = "firrtl.passes.InlineAnnotation"}]} {
%test_wire = firrtl.wire : !firrtl.uint<2>
firrtl.instance test2 sym @sym @test2()
firrtl.instance test3 @test3()
}
firrtl.module private @test2() attributes {annotations =
[{class = "firrtl.passes.InlineAnnotation"}]} {
%test_wire = firrtl.wire : !firrtl.uint<2>
firrtl.instance test3 sym @sym @test3()
}
firrtl.module private @test3() {
%test_wire = firrtl.wire : !firrtl.uint<2>
}
}

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