[LowerFirReg] Reimplement the mux reachability analysis #6709
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mikeurbach
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WIP wip wip Fix lit test Fixup
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Thanks for all the feedback. Finally merged this PR and sorry for the delay, I just realized it was still open. |
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This implements a new heuristic to determine if a Mux is reachable from a FirReg. In general an operation is reachable from a register if its in the fanout of the register. For FirReg lowering, an if/else structure is required for proper enable inference, if a mux is within the fanout from the register. The fanout path can only consist of MuxOp, ArrayGetOp or ArrayCreateOp. Thus any ops other than MuxOp, ArrayGetOp or ArrayCreateOp block the reachability. The analysis is built lazily when its queried and the result is cached to avoid redundant traversal of the IR. This fixes an issue that caused the merged commit for #6709 to be reverted. The was to explicitly specify the default size of `SmallVector`.
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The PR implements a new heuristic to determine if a Mux is reachable from a FirReg. In general an operation is reachable from a register if its in the fanout of the register. For FirReg lowering, an if/else structure is required for proper enable inference, if a mux is within the fanout from the register. The fanout path can only consist of MuxOp, ArrayGetOp or ArrayCreateOp. Thus any ops other than MuxOp, ArrayGetOp or ArrayCreateOp block the reachability. The analysis is built lazily when its queried and the result is cached to avoid redundant traversal of the IR.
cepheus69
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Apr 22, 2024
This implements a new heuristic to determine if a Mux is reachable from a FirReg. In general an operation is reachable from a register if its in the fanout of the register. For FirReg lowering, an if/else structure is required for proper enable inference, if a mux is within the fanout from the register. The fanout path can only consist of MuxOp, ArrayGetOp or ArrayCreateOp. Thus any ops other than MuxOp, ArrayGetOp or ArrayCreateOp block the reachability. The analysis is built lazily when its queried and the result is cached to avoid redundant traversal of the IR. This fixes an issue that caused the merged commit for llvm#6709 to be reverted. The was to explicitly specify the default size of `SmallVector`.
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The PR implements a new heuristic to determine if a Mux is reachable from a FirReg.
In general an operation is reachable from a register if its in the fanout of the register.
For FirReg lowering, an if/else structure is required for proper enable inference, if a mux is within the fanout from the register.
The fanout path can only consist of
MuxOp,ArrayGetOporArrayCreateOp.Thus any ops other than
MuxOp,ArrayGetOporArrayCreateOpblock the reachability.The analysis is built lazily when its queried and the result is cached to avoid redundant traversal of the IR.