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[LowerFirReg] Reimplement the mux reachability analysis #6914

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merged 19 commits into from
Apr 11, 2024

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prithayan
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@prithayan prithayan commented Apr 11, 2024

Reopened the PR #6709 , after fixing the issue that required the merged
commit to be reverted.

This implements a new heuristic to determine if a Mux is reachable from a
FirReg. In general an operation is reachable from a register if its in the
fanout of the register. For FirReg lowering, an if/else structure is required
for proper enable inference, if a mux is within the fanout from the register.
The fanout path can only consist of MuxOp, ArrayGetOp or ArrayCreateOp.
Thus any ops other than MuxOp, ArrayGetOp or ArrayCreateOp block the
reachability. The analysis is built lazily when its queried and the result is
cached to avoid redundant traversal of the IR.

@prithayan prithayan merged commit 442e886 into main Apr 11, 2024
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@uenoku
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uenoku commented Apr 11, 2024

What was the issue and fix here?

@dtzSiFive
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What was the issue and fix here?

Windows builder specifically errored because the SmallVector's element size crossed a threshold.
(maybe std::function size? not sure)

CI build failure (Windows doesn't run on PR's but was promptly reverted until fixed (thanks!)):
https://github.com/llvm/circt/actions/runs/8622542911/job/23633892020

Looks like fix was doing what was asked by that error and explicitly specifying number of elements to allocate, here:

8350b0d

@prithayan
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Thanks @dtzSiFive , that's right. The issue was default vector size, which was fixed in the commit.

@prithayan prithayan deleted the dev/pbarua/improve-lower-seq-to-sv branch April 11, 2024 15:28
@uenoku
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uenoku commented Apr 11, 2024

Thanks, just wanted to make sure what was going on :) Thank you for the details.

cepheus69 pushed a commit to cepheus69/circt that referenced this pull request Apr 22, 2024
This implements a new heuristic to determine if a Mux is reachable from a
FirReg. In general an operation is reachable from a register if its in the
fanout of the register. For FirReg lowering, an if/else structure is required
for proper enable inference, if a mux is within the fanout from the register.
The fanout path can only consist of MuxOp, ArrayGetOp or ArrayCreateOp.
Thus any ops other than MuxOp, ArrayGetOp or ArrayCreateOp block the
reachability. The analysis is built lazily when its queried and the result is
cached to avoid redundant traversal of the IR.
This fixes an issue that caused the merged commit for llvm#6709 to be reverted.
The was to explicitly specify the default size of `SmallVector`.
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3 participants