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[LowerFirReg] Reimplement the mux reachability analysis #6914
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WIP wip wip Fix lit test Fixup
What was the issue and fix here? |
Windows builder specifically errored because the SmallVector's element size crossed a threshold. CI build failure (Windows doesn't run on PR's but was promptly reverted until fixed (thanks!)): Looks like fix was doing what was asked by that error and explicitly specifying number of elements to allocate, here: |
Thanks @dtzSiFive , that's right. The issue was default vector size, which was fixed in the commit. |
Thanks, just wanted to make sure what was going on :) Thank you for the details. |
This implements a new heuristic to determine if a Mux is reachable from a FirReg. In general an operation is reachable from a register if its in the fanout of the register. For FirReg lowering, an if/else structure is required for proper enable inference, if a mux is within the fanout from the register. The fanout path can only consist of MuxOp, ArrayGetOp or ArrayCreateOp. Thus any ops other than MuxOp, ArrayGetOp or ArrayCreateOp block the reachability. The analysis is built lazily when its queried and the result is cached to avoid redundant traversal of the IR. This fixes an issue that caused the merged commit for llvm#6709 to be reverted. The was to explicitly specify the default size of `SmallVector`.
Reopened the PR #6709 , after fixing the issue that required the merged
commit to be reverted.
This implements a new heuristic to determine if a Mux is reachable from a
FirReg. In general an operation is reachable from a register if its in the
fanout of the register. For FirReg lowering, an if/else structure is required
for proper enable inference, if a mux is within the fanout from the register.
The fanout path can only consist of MuxOp, ArrayGetOp or ArrayCreateOp.
Thus any ops other than MuxOp, ArrayGetOp or ArrayCreateOp block the
reachability. The analysis is built lazily when its queried and the result is
cached to avoid redundant traversal of the IR.