Notes on the Red Pitaya Open Source Instrument

Xilinx PCIe to MIG DDR4 example designs and custom part data files

RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.

CNN accelerator

This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit

A Tcl-Library for scripted HDL generation

Controller module for RISC-V core CI/CD

A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.

Example of a full DC synthesis script for a simple design

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

A small FPGA and APSoC project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. Refresh of fpga-serial-acl-tester-1 and -2.

All about FPGA...

Hardware integer divider module

Implementation of Timing Exceptions in RTL design for STA

System Verilog and Arduino Code that lets the user enter and send 8-bit binary using the Basys 3 switches and buttons to be converted to ASCII and displayed on an LCD.

Matrix base operations on FPGA example

МИЭТ, курс "Архитектуры процессорных систем"

WARC Open Fusesoc Cores Repository

PDM Microphone peripheral written in SystemVerilog HDL

Implementing a parking slot system usingRTL Coding, the PYNQ Z2 board, seven-segment display, wires, and a breadboard.