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Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Here are 137 public repositories matching this topic...

verilator

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

Updated Nov 2, 2025
C++

google / xls

XLS: Accelerated HW Synthesis

open-source compiler hls pipeline verilog high-level-synthesis mid-level-synthesis

Updated Nov 1, 2025
C++

verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

fpga routing eda cad verilog synthesis placement vtr vpr

Updated Nov 2, 2025
C++

metroboy

aappleby / metroboy

A repository of gate-level simulators and tools for the original Game Boy.

emulator simulator gameboy gameboy-emulator verilog hdl

Updated Feb 23, 2025
C++

MikePopoloski / slang

SystemVerilog compiler and language services

parse compiler slang verilog language-service systemverilog

Updated Nov 2, 2025
C++

jks-prv / Beagle_SDR_GPS

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS (archived)

open-source fpga gps pcb verilog sdr web-interface vlf cape hf beagle shortwave 14-bit-adc

Updated Dec 3, 2024
C++

vmware-archive / cascade

A Just-In-Time Compiler for Verilog from VMware Research

fpga hardware repl jit verilog just-in-time

Updated Jul 1, 2021
C++

chipsalliance / Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi antlr4-grammar parser-ast vpi-api vpi-standard

Updated Sep 6, 2025
C++

Nic30 / hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

python parser fpga vhdl verilog systemverilog vhdl-parser antrl4 systemverilog-parser verilog-parser

Updated Jun 30, 2025
C++

Degate

DegateCommunity / Degate

A modern and open-source cross-platform software for chips reverse engineering.

security multi-platform gui cross-platform cpp vhdl reverse-engineering cybersecurity verilog chips vlsi security-tools

Updated Nov 25, 2024
C++

ZipCPU / dblclockfft

A configurable C++ generator of pipelined Verilog FFT cores

fpga gplv3 verilog fft verilog-components verilator

Updated Apr 18, 2024
C++

ZipCPU / autofpga

A utility for Composing FPGA designs from Peripherals

c-plus-plus fpga verilog wishbone verilator wishbone-bus

Updated Dec 23, 2024
C++

aappleby / metron

A C++ to Verilog translation tool with some basic guarantees that your code will work.

c fpga compiler cpp transpiler verilog hdl

Updated Feb 23, 2025
C++

nitram2342 / degate

Open source software for chip reverse engineering.

visualization gui library vhdl reverse-engineering image-processing verilog chip image-recognition vlsi

Updated Sep 22, 2020
C++

esonghori / TinyGarble

TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits

security-protocol verilog garbled-circuits circuit-description

Updated Nov 14, 2023
C++

ZipCPU / cordic

A series of CORDIC related projects

fpga dsp verilog dds cordic

Updated Nov 12, 2024
C++

nlsynth / karuta

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

programming-language fpga verilog iroha

Updated Jan 29, 2022
C++

ben-marshall / verilog-vcd-parser

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

parser simulation vhdl trace verilog systemverilog vcd

Updated Mar 6, 2022
C++

ultraembedded / core_sdram_axi4

SDRAM controller with AXI4 interface

fpga verilog sdram-controller axi4

Updated Aug 8, 2019
C++

ultraembedded / core_ft60x_axi

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

fpga data-acquisition verilog bus-master ftdi-devices usb3 xilinx-fpga axi4 ft600

Updated Jun 6, 2020
C++

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Website: github.com/topics/verilog
Wikipedia: Wikipedia