verilog-parser

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Here are 5 public repositories matching this topic...

Nic30 / hdlConvertor

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Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

python parser fpga vhdl verilog systemverilog vhdl-parser antrl4 systemverilog-parser verilog-parser

Updated Jun 30, 2025
C++

codinuum / cca

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Code Continuity Analysis Framework

semantic-web ontology software-engineering java-parser python-parser syntax-aware cpp-parser verilog-parser ast-differencing ast-patching fortran-parser ast-diff-tool ast-patch-tool ast-matching

Updated Mar 3, 2025
OCaml

PaletiKrishnasai / VLSI_Practice

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work done as part of VLSI Design practice course

register verilog xilinx vlsi wallace-tree-multiplier array-multiplication sklansky-adder dadda-tree recursive-doubling-cla ripple-carry-adder parity-generator verilog-parser

Updated Feb 21, 2021
Verilog

CLI tools to extract and display port definitions from Verilog files and generate repository file-trees to make navigation and interaction with my hardware projects easier for anyone. Automatically fetched as utils package along any of my repository downloads through download_repos.bat/.sh scripts that are hosted on each repo 😄.

cli parser eda rtl hdl verilog-hdl filetree cli-tool verilog-parser utils-tools markdown-output port-extraction default-box-output repo-filetree-generator

Updated Apr 11, 2026
Shell

Joyeastronautic923 / portmap-HDL

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Extract and display Verilog port definitions in a clean CLI table for fast module inspection and documentation

cli parser eda rtl verilog-hdl filetree cli-tool verilog-parser utils-tools markdown-output port-extraction default-box-output repo-filetree-generator

Updated Apr 15, 2026
Lua

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verilog-parser

Here are 5 public repositories matching this topic...

Nic30 / hdlConvertor

codinuum / cca

PaletiKrishnasai / VLSI_Practice

KARAN-D05 / portmap-HDL

Joyeastronautic923 / portmap-HDL

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