Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
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PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
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Jan 11, 2025 - JavaScript
🌳 The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
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Sep 17, 2022 - JavaScript
SystemVerilog grammar for tree-sitter
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Nov 11, 2024 - JavaScript
Playground for VGA projects on Tiny Tapeout
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Sep 21, 2025 - JavaScript
HTML & Js based VCD viewer
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Aug 1, 2025 - JavaScript
A lightweight IDE that supports verilog simulation and RISC-V code compilation
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Jul 26, 2022 - JavaScript
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
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Jul 18, 2020 - JavaScript
🔁 elastic circuit toolchain
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Dec 2, 2024 - JavaScript
Source code for Web-Based Verilog Simulation Platform in ECE 27000 at Purdue University
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Jul 2, 2025 - JavaScript
Verilog HDL implementations of adders/subtractor, multiplier, divider and square root. As well as HTML simulations.
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Apr 29, 2022 - JavaScript
design hierarchy inspector React component
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Apr 20, 2021 - JavaScript
Control a FPGA via a Raspberry Pi and a Webserver.
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Apr 20, 2025 - JavaScript
A playground based on the classic version of the Cloud V IDE
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Mar 23, 2021 - JavaScript
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