Essenceia / low-latency-ethernet Star 50 Code Issues Pull requests RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project. fpga tcp udp rtl verilog ethernet hft 10gbit 10gbase-r Updated Jan 10, 2024 Verilog
Essenceia / ethernet-physical-layer Star 32 Code Issues Pull requests RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R. c fpga rtl verilog ethernet iverilog vpi pcs 10gbase-r 40gbase-r Updated Jan 2, 2024 Tcl
theSergeyGusev / simple10GbaseR Star 10 Code Issues Pull requests FPGA Low latency 10GBASE-R PCS fpga ieee80211 pcs 10g 10gbase-r 10gbps Updated May 23, 2023 SystemVerilog