A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
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Nov 19, 2025 - SystemVerilog
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rtl-design
Here are 14 public repositories matching this topic...
JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.
asic rtl verilog finite-state-machine uart alu hdl verilog-hdl open-source-hardware serial-communication rtl-design digital-designs 8bit-cpu chip-design tinytapeout control-logic prototype-core embedded-core minimal-cpu-core
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Oct 19, 2025 - SystemVerilog
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
makefile verilog synthesis systemverilog hdl testbench systemverilog-hdl systemverilog-simulation rtl-design systemverilog-test-bench edge-detector-with-mealy
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Nov 6, 2022 - SystemVerilog
BDD Gherkin implementation in native SystemVerilog, based on UVM.
asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification
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Nov 16, 2024 - SystemVerilog
Getting started with SystemVerilog: Hardware Description Language for design and verification.
testing design asic fpga hardware verification rtl systemverilog hardware-designs hdl modelsim questasim uvm testbench systemverilog-hdl rtl-design uvm-verification
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Nov 5, 2025 - SystemVerilog
Verification of D-FF using UVM on EDA playground
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Nov 19, 2023 - SystemVerilog
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
asic fpga rtl systemverilog verilog-hdl xilinx-vivado multiplier fpga-programming vlsi-design asic-design rtl-design parallel-multiplication systemverilog-test-bench register-transfer-level
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Jun 19, 2025 - SystemVerilog
A collection of systemverilog designs implemented on AMD Vivado tool
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Nov 21, 2025 - SystemVerilog
A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.
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Nov 5, 2025 - SystemVerilog
UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.
fpga eda uart systemverilog vlsi uvm testbench digital-design serial-communication apb functional-verification hardware-verification rtl-design rtl-verification uvm-environment
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Nov 1, 2025 - SystemVerilog
An open source SoC project for the VLSI 2 class at ETHZ. Selected as one of the best design and taped out in IHP 130nm technology
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Nov 16, 2025 - SystemVerilog
Processor Design of RV32I 5-Stage Pipelined CPU
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Jul 4, 2024 - SystemVerilog
Parameterizable Asynchronous FIFO with Gray Code Synchronization - A robust clock domain crossing solution in SystemVerilog
asic fpga verilog systemverilog fifo digital-design gray-code clock-domain-crossing asynchronous-fifo rtl-design
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Nov 20, 2025 - SystemVerilog
Processor Design of RV32I Single Cycle CPU
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Apr 28, 2024 - SystemVerilog
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