VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a stateful, zero-dependency LLM orchestration skill. Features sub-agent nesting for code gen and behavioral-driven verification.

RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

VeriFlow-Agent: Agent-based RTL Design Pipeline A LangGraph-powered RTL design automation tool that transforms hardware design from manual coding to agent-based workflows. Features 7-stage pipeline (Architect → Synthesis), multi-backend LLM support (Claude/Anthropic/LangChain), and three interfaces: Claude Code Agent, Web UI, and CLI.

A 4-way Smart Traffic Light Controller using Verilog HDL with a real-time Digital Twin simulation built in Python/Streamlit.

Hardware-level image processing accelerator (RGB to Grayscale) in SystemVerilog using AXI4-Stream, verified via Python & Cocotb co-simulation.

Browser-based RTL design environment — natural language → Verilog generation → testbench auto-generation → Icarus Verilog simulation → autonomous bug correction

This is a pipeline cpu designed to support RISC-V ISA.

IEEE 754 half-precision (FP16) FPU in Verilog — implements Add, Sub, Mul, Div with a Python/NumPy verification pipeline. Achieves 99.7% accuracy across 10,000 randomised test cases including subnormals, overflow, and NaN edge cases.

A digital cookbook with an editorial feel. Guided cooking, real grocery costs, in Arabic and English.