5-stage-pipelined-processor

Here are 6 public repositories matching this topic...

arhamhashmi01 / rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

vhdl verilog microprocessor vivado hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator rv32im asic-design chip-design 5-stage-pipelined-processor rv32i-processor

Updated Feb 19, 2025
Verilog

arhamhashmi01 / rv32i-sv

Star

This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog

microprocessor systemverilog hardware-designs risc-v rv32i systemverilog-hdl 5-stage-pipeline 5-stage-pipelined-processor

Updated Jun 10, 2024
SystemVerilog

chanbengz / SUSTech_CS202_Project_MineCPU

Star

RISC-V 5-Stage Pipeline CPU, Semester Project of CS202 Computer Organization

riscv computer-organization difftest 5-stage-pipelined-processor

Updated Dec 30, 2024
SystemVerilog

Mahekkumar-Varasada / 5-Stage-MIPS-Pipelined-with-Hazard-Mitigation

Star

The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.

mips computer-architecture hazard-detection mips-architecture mips32 nirma-university forwarding-unit control-hazards 5-stage-pipelined-processor hazard-mitigation