5-stage-pipelined-processor

Here are 3 public repositories matching this topic...

arhamhashmi01 / rv32i-pipeline-processor

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

vhdl verilog microprocessor vivado hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator rv32im asic-design chip-design 5-stage-pipelined-processor rv32i-processor

Updated Feb 19, 2025
Verilog

akira2963753 / MIPS-5-stage-pipelined-CPU

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This is NTUST-EE 2025 Computer Organization, the course's final project is the implementation of the 5-stage pipelined cpu based on mips.

cpu mips mips-cpu 5-stage-pipelined-processor

Updated Aug 12, 2025
Verilog

Mahekkumar-Varasada / 5-Stage-MIPS-Pipelined-with-Hazard-Mitigation

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The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.

mips computer-architecture hazard-detection mips-architecture mips32 nirma-university forwarding-unit control-hazards 5-stage-pipelined-processor hazard-mitigation

Updated Oct 27, 2024
Verilog

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