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1. The-Cadence-Files The-Cadence-Files Public

   A collection of all the projects implemented on Cadence Virtuoso

   2

2. The-RTL-Files The-RTL-Files Public

   A collection of systemverilog designs implemented on AMD Vivado tool

   SystemVerilog 1

3. Valentine-s-Day Valentine-s-Day Public

   A website to ask out your valentine... 👀🤍

   HTML

4. 8-bit-ALU 8-bit-ALU Public

   8-bit Arithmetic Logical Unit (ALU) Implemented in SystemVerilog using Xilinx Vivado tool

   SystemVerilog

5. Food-Delivery-Time-Prediction Food-Delivery-Time-Prediction Public

   To predict food delivery times based on customer location, restaurant location, weather, traffic, and other factors

   Jupyter Notebook

6. RISC-V-CPU-Core RISC-V-CPU-Core Public

   Built a RISC-V CPU Core using Transaction-Level Verilog

   TL-Verilog