Skip to content

An open source SoC project for the VLSI 2 class at ETHZ. Selected as one of the best design and taped out in IHP 130nm technology

License

Notifications You must be signed in to change notification settings

GiulioDeveloper/crocodilo

Repository files navigation

Crocodilo System-on-Chip

Chip Specifications

Crocodilo layout

Field Value
Application Pulp
Technology 130
Manufacturer IHP
Type Teaching
Package QFN56
Dimensions 2235 µm × 2235 µm
Gates 350 kGE
Voltage 1.2 V
Power 47.4 mW @ 80 MHz
Clock 80 MHz

Description

Modern embedded systems often require real-time processing of error-corrected sensor streams. Crocodilo accelerates a workload of this kind, built around three main stages:

  1. Decoding a signal composed of 64 samples of 32-bit words, protected with a Hamming (32, 26) Error-Correction Code (ECC).
  2. Computing an FFT (Fast Fourier Transform) on the decoded signal.
  3. Encoding the processed signal using the same Hamming ECC scheme.

A full software implementation of the workload was first developed to run on the original Croc design (with minor modifications), serving as a baseline. The hardware was then enhanced in four key ways:

  • A custom memory-mapped ECC accelerator added to the user domain of the SoC.
  • A fast multiplier integrated into the CVE2 core.
  • SRAM capacity increased to 16 KB.
  • Clock frequency raised to 94.3 MHz through timing optimizations.

The full description of the project can be found in the final report

Results

Crocodilo achieves a 37× speed-up on the real-time signal-processing workload, reducing end-to-end latency from 5.2 ms to 142 μs. This gain is driven by:

  • A single-cycle ECC accelerator, improving encode/decode throughput by over 40×.
  • A fast multiplier unit, accelerating the FFT stage by nearly 30×.
  • Expanded 16 KB SRAM, enabling the full memory footprint of the application.
  • A higher operating frequency of 94.3 MHz.

Project Context

This chip was designed as part of the VLSI design course at ETH Zurich which uses a (mostly) open source design flow for its exercises. Students are required to modify a Croc based SoC to improve its capabilities somehow to pass the course. This was one of the top-rated designs from the course and has been sent to manufacturing.

This work received generous support from the Leibniz Institute for High Performance Microelectronics through the BMBF project FMD-QNC (16ME0831).

About

An open source SoC project for the VLSI 2 class at ETHZ. Selected as one of the best design and taped out in IHP 130nm technology

Topics

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published