VeeR EH1 core

VeeR EL2 Core

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

Virtio implementation in SystemVerilog

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

Universal Verification Methodology (UVM) base libraries, with edits for Verilator

Extended and external tests for Verilator testing

SystemVerilog implemention of QEMU PCI edu device

Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

Superscalar dual-issue RISC-V processor

NESystem Verilog

Experimental RISCV implementation

Classic Pacman Implementation on a Xilinx FPGA! Simulated with Verilator + SFML

AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

ucrv32 is a simple educational RV32I microcontroller featuring a 5-stage pipeline architecture. Written in SystemVerilog and equipped with simulation support via Verilator, it offers a practical platform for learning digital design and computer architecture concepts.