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HaDes-V

tscheipel / HaDes-V

Star 92

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design
  • Updated Jun 5, 2025
  • SystemVerilog

UNLINEARITY / Atlas-of-Control-and-AI

Star 79

You may learn everything you want to know in this repository, concerning math, automation, computer science, and so on.่ฟ™ๆ˜ฏไธ€ไธช่‡ดๅŠ›ไบŽๆž„ๅปบไปฅๆ•ฐ็†็Ÿฅ่ฏ†ไธบๆ นๅŸบ็š„๏ผŒๅŒ…ๅซไธ€ๅˆ‡็š„ๅบ“(Learn Everything๏ผ)ๆถต็›–่‡ชๅŠจๅŒ–็š„ๅญฆไน ๏ผŒ่‡ชๅŠจๆŽงๅˆถๅŽŸ็†ใ€ๆ•ฐๅญฆใ€็‰ฉ็†ใ€็”ตๆœบใ€ๅปบๆจก......ๆŒ็ปญๆ›ดๆ–ฐไธญ๏ผ

learning website math robotics computer knowledge-graph control-theory university-course 3d-graph
  • Updated Nov 19, 2025
  • Markdown

Hazrat-Ali9 / Software-Engineering-at-University

Star 30

๐Ÿฒ University-level Software ๐Ÿณ Engineering courses ๐Ÿฆ theory to practical ๐Ÿ… implementation this ๐Ÿซ‘ repo bridges the ๐Ÿ” gap between academia ๐Ÿš‚ and real-world ๐Ÿšž development Software ๐Ÿš’ Development Life Cycle Agile ๐Ÿšž UML Design Patterns ๐Ÿš˜ Testing and Maintenance ๐Ÿš notes assignments studies โœˆ and project templates analysis software design team๐Ÿšค

python testing programming university university-project software software-engineering software-development software-testing university-course software-engineer
  • Updated Sep 27, 2025

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