An abstraction library for interfacing EDA tools

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)

SimIO is a collection of virtualized components to interact with a (System)Verilog simulation.

🪀 Tool to play with HDL (inspired by EdaPlayground)

Tests your ECE 320 Single Cycle RISC-V Processor: Up to PD5

Python/PyPI wrapper for Verilator