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1. friscv friscv Public

   RISCV CPU implementation in SystemVerilog

   SystemVerilog 20 4

2. svut svut Public

   SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

   Python 70 16

3. bster bster Public

   Implementation of a binary search tree algorithm in a FPGA/ASIC IP

   SystemVerilog 14 4

4. async_fifo async_fifo Public

   A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

   Verilog 261 76

5. axi-crossbar axi-crossbar Public

   An AXI4 crossbar implementation in SystemVerilog

   SystemVerilog 123 26

6. svlogger svlogger Public

   SystemVerilog Logger

   SystemVerilog 16 1