A small, light weight, RISC CPU soft core
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Nov 30, 2024 - Verilog
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verilator
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RISC-V CPU Core (RV32IM)
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Sep 18, 2021 - Verilog
32-bit Superscalar RISC-V CPU
linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors
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Sep 18, 2021 - Verilog
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain
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Apr 30, 2024 - Verilog
A simple, basic, formally verified UART controller
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Jan 29, 2024 - Verilog
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface
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Jan 4, 2025 - Verilog
A wishbone controlled scope for FPGA's
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Jan 12, 2024 - Verilog
Digital Interpolation Techniques Applied to Digital Signal Processing
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Jun 24, 2024 - Verilog
Wishbone controlled I2C controllers
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Nov 12, 2024 - Verilog
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
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Oct 27, 2022 - Verilog
Re-coded Xilinx primitives for Verilator use
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Mar 1, 2024 - Verilog
A collection of debugging busses developed and presented at zipcpu.com
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Jan 18, 2024 - Verilog
SCARV: a side-channel hardened RISC-V platform
open-source cryptography cpu crypto riscv verilog research-project mit-license ise formal-verification yosys instruction-set-architecture verilator riscv32 xcrypto
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Jan 11, 2023 - Verilog
A ZipCPU SoC for the Nexys Video board supporting video functionality
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Nov 13, 2024 - Verilog
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