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verilator

Here are 41 public repositories matching this topic...

ultraembedded / riscv

RISC-V CPU Core (RV32IM)

asic cpu fpga verification verilog pipeline-processor risc-v rv32i verilator riscv-linux rv32im

Updated Sep 18, 2021
Verilog

ZipCPU / zipcpu

A small, light weight, RISC CPU soft core

cpu fpga verilog cross-compiler wishbone soft-core verilator zipcpu wishbone-bus risc-cpu

Updated Aug 9, 2025
Verilog

ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

ultraembedded / cores

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Sep 16, 2025
Verilog

ZipCPU / sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface

Updated Apr 24, 2025
Verilog

ZipCPU / wbuart32

A simple, basic, formally verified UART controller

fpga verilog uart serialport uart-verilog wishbone verilator wishbone-bus

Updated Jan 29, 2024
Verilog

ZipCPU / vgasim

A Video display simulator

video fpga gplv3 verilog gtkmm vga verilator video-simulator

Updated May 16, 2025
Verilog

ZipCPU / openarty

An Open Source configuration of the Arty platform

fpga fpga-soc wishbone verilator arty zipcpu wishbone-bus

Updated Jan 17, 2024
Verilog

chili-chips-ba / wireguard-fpga

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

embedded fpga iss vpn rtl verilog risc-v wireguard verilator cocotb vproc

Updated Sep 19, 2025
Verilog

ZipCPU / dpll

A collection of phase locked loop (PLL) related projects

fpga gplv3 verilog verilator pll

Updated Jan 18, 2024
Verilog

ZipCPU / wbscope

A wishbone controlled scope for FPGA's

fpga verilog debugging-tools wishbone verilator wishbone-bus

Updated Jan 12, 2024
Verilog

ZipCPU / interpolation

Digital Interpolation Techniques Applied to Digital Signal Processing

fpga interpolation dsp verilog verilator interpolation-methods interpolation-techniques

Updated Jun 24, 2024
Verilog

ZipCPU / wbi2c

Wishbone controlled I2C controllers

fpga i2c gplv3 verilog verilator i2c-slave wishbone-bus i2c-master

Updated Nov 12, 2024
Verilog

fredrequin / verilator_xilinx

Re-coded Xilinx primitives for Verilator use

fpga verilog xilinx-fpga verilator

Updated Jun 24, 2025
Verilog

ZipCPU / zbasic

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems

fpga verilog system-on-chip verilator zipcpu

Updated Oct 27, 2022
Verilog

ZipCPU / s6soc

CMod-S6 SoC

fpga fpga-soc wishbone verilator zipcpu wishbone-bus

Updated Jan 6, 2018
Verilog

ZipCPU / dbgbus

A collection of debugging busses developed and presented at zipcpu.com

verilog debugging-tools wishbone fgpa verilator wishbone-bus

Updated Jan 18, 2024
Verilog

nju-mips / noop-lo

A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.

gpio fpga sbt mips vivado uart noop verilator

Updated Feb 10, 2020
Verilog

scarv / scarv-cpu

SCARV: a side-channel hardened RISC-V platform

open-source cryptography cpu crypto riscv verilog research-project mit-license ise formal-verification yosys instruction-set-architecture verilator riscv32 xcrypto

Updated Jan 11, 2023
Verilog

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