A place to keep my synthesizable verilog examples.

Quickstart guide on Icarus Verilog.

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

Implementation of 5 Stage 32I RISC V Pipeline Processor.

This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.

Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL

Learning Path: RISC-V System-on-Chip (SoC) design, from Register Transfer Level (RTL) to a GDSII layout | Complete VLSI design flow using open-source EDA tools.

16-bit Slansky Adder design using verilog HDL

A completely functional encryption decryption model with specially generated Asymmetric key verification

This repository consists of Load, Store and Read word data paths using a Single Cycle Core.

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

Pre and Post Synthesis Simulation of a Design VSDMemSOC

Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.

Verilog is a hardware description language. This repo is basically a learning journey of verilog

An iverilog program displaying the working of RING and JOHNSONS counter with the Timing diagram in GTK wave.

This is a simple FIFO queue implementation in Verilog for the Modern Computer Architectures course (2016-2017) of Harokopio University.

Practice Codes of Verilog Language

The Samsung RISC-V Workshop offers hands-on training in SoC design using the VSD Squadron Mini board, covering RISC-V ISA, toolchains, and system design, with an industry-recognized certification.

This project focuses on the design and implementation of a 4-bit Arithmetic Logic Unit (ALU) using reversible logic gates such as Feynman, Peres, and Fredkin gates. Reversible logic is efficient due to its applications in low-power digital design, quantum computing, and nanotechnology.