Scala based HDL

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

Open source machine learning accelerators

An exquisite superscalar RV32GC processor.

CNN accelerator implemented with Spinal HDL

Antmicro's fast, vendor-neutral DMA IP in Chisel

A RISC-V Core (RV32I) written in Chisel HDL

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

A reimplementation of a tiny stack CPU

An High-Performance SLAM Hardware Accelerator Implementation for FPGA

HyperDbg's logic analyzer and chip-level hardware debugger

SpinalHDL - Cryptography libraries

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.

shdl6800: A 6800 processor written in SpinalHDL

CNN accelerator implemented with Spinal HDL

An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"