AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Send video/audio over HDMI on an FPGA

VeeR EH1 core

Project F brings FPGAs to life with exciting open-source designs you can build on.

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

VeeR EL2 Core

Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

NES for the Analogue Pocket

Методические материалы по разработке процессора архитектуры RISC-V

Atari STE MiSTery core for the Tang Nano FPGAs

An AXI4 crossbar implementation in SystemVerilog

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Collection of IP and information on how to develop for openFPGA and Analogue Pocket

AMD OpenNIC Shell includes the HDL source files

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA [FCCM 20]

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.