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Pull requests: SpinalHDL/SpinalHDL

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Pull requests list

Implement automatic initial reset and signal analysis in Verilator ba…
#1806 opened Sep 11, 2025 by jaynerlin Loading…
2 tasks done
10
AFix resize() bug
#1801 opened Sep 9, 2025 by thajohns Loading…
2 tasks done
add AFix contructors from width and resolution
#1800 opened Sep 9, 2025 by thajohns Loading…
2 tasks done
Add RoundType.NONE
#1798 opened Sep 9, 2025 by thajohns • Draft
2 tasks
Add random isolation test suites for SpinalHDL and Verilator
#1787 opened Aug 15, 2025 by jaynerlin Loading…
2 tasks
3
Add Workaround for RAM with init values in sim
#1777 opened Aug 4, 2025 by g0t00 Loading…
1 of 2 tasks
10
Fix path where waves get stored for IVerilog and Ghdl backends
#1747 opened Jun 17, 2025 by louiecaulfield Loading…
2 tasks
Fix width inferr
#1746 opened Jun 17, 2025 by Readon Loading…
1 of 2 tasks
1
1
Switch emit rework
#1724 opened May 5, 2025 by Dolu1990 Loading…
5
Change AFix division
#1722 opened May 2, 2025 by thajohns Loading…
1 of 2 tasks
4
Create IMasterSlaveDirDeclare
#1676 opened Mar 11, 2025 by g0t00 Loading…
1 of 2 tasks
4
Interface-related SystemVerilog Code Emission Enhancements
#1631 opened Dec 23, 2024 by fl4shk • Draft
2 tasks
4
Fix simulation failure with Verilator v5.x on Windows
#1618 opened Dec 10, 2024 by du33169 Loading…
2 tasks
1
7
Make 2.11 & 2.13 CI test always.
#1589 opened Nov 5, 2024 by Readon • Draft
1 task
2
fix test initial value problem for Dfi Controller.
#1581 opened Oct 29, 2024 by Readon Loading…
2 tasks
1
Add mill template link to readme
#1505 opened Aug 13, 2024 by mrcmry Loading…
2
Add SamplerCC pushCd(reg) -> popCd(BufferCC)
#1500 opened Aug 5, 2024 by Dolu1990 Loading…
set rst name for default clock domain by ClockDomainConfig
#1484 opened Jul 17, 2024 by yportne13 Loading…
3
RFC: Add blackboxing for simple 1-port synchronous ROMs
#1475 opened Jul 11, 2024 by bunnie Loading…
2 tasks
20
ACE & ACE-Lite support
#1450 opened Jun 12, 2024 by KireinaHoro • Draft
3 of 8 tasks
5
Bugfix/wb pipelined
#1375 opened Mar 26, 2024 by jdavidberger Loading…
1
71
Ability to remap address for BusSlaveFactory
#1354 opened Mar 13, 2024 by KireinaHoro • Draft
2 tasks
14
Verilog generated when using synchronous resets is not understood by SymbiYosys - remove "assert() else begin end"-block generation for now
#1315 opened Feb 19, 2024 by janschiefer Loading…
1
TaggedUnion implementation
#1241 opened Nov 10, 2023 by ronan-lashermes Loading…
2 tasks
35
[feature] FuseSocGeneratorBuilder provide a easy way to use fusesoc
#1232 opened Nov 2, 2023 by chenbo-again Loading…
27
ProTip! What’s not been updated in a month: updated:<2025-08-19.