opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Open source FPGA-based NIC and platform for in-network compute

Must-have verilog systemverilog modules

HDL libraries and projects

SERV - The SErial RISC-V CPU

The Ultra-Low Power RISC-V Core

RISC-V CPU Core (RV32IM)

A small, light weight, RISC CPU soft core

The USRP™ Hardware Driver Repository

32-bit Superscalar RISC-V CPU

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

An Open-source FPGA IP Generator

🌱 Open source ecosystem for open FPGA boards

RISC-V Linux SoC, marchID: 0x2b

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

Various HDL (Verilog) IP Cores

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed) device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

An open source library for image processing on FPGA.