Must-have verilog systemverilog modules

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

Asynchronous FIFO for transferring data between two asynchronous clock domains

FIFO implementation with different clock domains for read and write.

RTL of a parametrized asynchronous FIFO that allows for variable depth, data width, and includes almost empty/full flags.

Collection of utility modules written in Verilog

A coocbook of HDL (primarily Verilog) modules

华中科技大学网络空间安全学院密码工程学基础2023(密码硬件工程)

Pipelined a real-time edge detection system with a OV7670 camera and Nexys A7 100T FPGA Trainer Board

All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.

UART Design with CDC, FIFO Buffers, and Dynamic Baud Rate Configuration

A project to implement and test synchronous and asynchronous FIFO using Questasim software.

codes of my IUT FPGA LAB

Eight different verilog projects are combined to creat a big custom asic project.

This Repository was created and aimed to study FIFO vs FWFT.

I have modelled a FIFO memory with depth of 16. The circuit is described using verilog language. I have also synthesized the design using an open source tool named Yosys, for performing technology mapping I have used a 45 nm pdk of a typical process- The library used NLDM modelling. I also performed logic optimization using Yosys using commands.

This Verilog project implements an I2C bus system with a master and three distinct slaves: Memory, FIFO, and LIFO.

Digital System Design Verilog Implementation

Verilog Mini Projects