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1. 16-bit-microprocessor-verilog 16-bit-microprocessor-verilog Public

   A final year undergraduate major project. (Dec 2019 - Mar 2020)

   C 2

2. fifo fifo Public

   A project to implement and test synchronous and asynchronous FIFO using Questasim software.

   Verilog 2

3. interrupt-controller interrupt-controller Public

   A project to implement and test interrupt controller using Questasim software.

   Verilog 2 1

4. Drug-Target-Interaction-Prediction-KNN- Drug-Target-Interaction-Prediction-KNN- Public

   A group project as a part of Pattern Classification course. (Oct 2021 - Nov 2021)

   1

5. SRAM-memory SRAM-memory Public

   A project to implement and test simple SRAM synchronous positive edge memory.

   SystemVerilog 1

6. dynamic-pattern-detector-verilog dynamic-pattern-detector-verilog Public

   A project to implement and test dynamic pattern detector using verilog in different ways.

   Verilog 1