Verilog Mini Projects

This repository currently consists of 10 mini projects.

FIFO

Synchronous FIFO

Module

module fifo #(parameter WIDTH=8, DEPTH=8)(
	input clk,
	input reset,
	input write,
	input read,
	input [WIDTH-1:0] data_in,
	output reg [WIDTH-1:0] data_out,
	output full,
	output empty
	);

Waveform

Asynchronous FIFO

Module

module asy_fifo #(parameter WIDTH=8, DEPTH=16)(
    input rd_clk,
    input wr_clk,
    input reset,
    input read,
    input write,
    input [WIDTH-1:0] data_in,
    output reg [WIDTH-1:0] data_out,
    output full,
    output empty
);

Waveform

LFSR

Module

module lfsr #(parameter DATA_WIDTH = 5)(
    input clk,
    input enable,
    input load,
    input [DATA_WIDTH-1:0] data_in,
    output [DATA_WIDTH-1:0] data_out,
    output done
);

Waveform

Alarm Clock

Module

module alarm_clock(
  input clk,				//10Hz clock 
 input areset,			        //Asynchronous reset
 input [1:0] hr_in_1,	    		//Most significant input hour digit
 input [3:0] hr_in_0,	    		//Least significant input hour digit
 input [3:0] min_in_1,	  		//Most significant input minute digit
 input [3:0] min_in_0,	  		//Least significant input minute digit
 input LD_alarm,		        //signal to set alarm
 input LD_time,			        //signal to set time 
 input STOP_alarm, 		    	//signal to stop alarm
 input AL_ON,			        //signal if alarm function is enable or not
 output [1:0] hr_out_1,	  		//Most significant output hour digit
 output [3:0] hr_out_0,   		//Least significant output hour digit
 output [3:0] min_out_1,  		//Most significant output minute digit
 output [3:0] min_out_0,  		//Least significant output minute digit
 output [3:0] sec_out_1,  		//Most significant output second digit
 output [3:0] sec_out_0,  		//Least significant output second digit
 output reg Alarm);		    	//alarm signal

Waveform

Barrel Shifter

Module

module barrel_shifter #(parameter WIDTH=8)(
    input [WIDTH-1:0] in,
    input [2:0] shift_amt,
    output reg [WIDTH-1:0] out
);

Waveform

Booth Multiplier

Module

module booth_mul(
	input signed [7:0] a,
	input signed [7:0] b,
	output signed [15:0] out
	);

Waveform

Carry Lookahead Adder

Module

module carry_lookahead_adder(
	input [3:0] a,
	input [3:0] b,
	input carry_in,
	output [3:0] sum,
	output carry_out
	);

Waveform

Sequence Detector

Module

module sequence_detector(
  input clk,
  input [3:0] in,
  output out);

Waveform

Traffic Light Controller

Module

module traffic_light_controller(
  input clk,
  output reg red,
  green,
  yellow);

Waveform

Vending Machine

Module

module vending_machine(
	input clk,
	input reset,
	input [1:0] product,
	input [5:0] amount,
	output reg product_1, product_2, product_3,
	output reg [4:0] balance
	);

Waveform

Voting Machine

Module

module voting_machine(
	 input clk,
	 input reset,
	 input [1:0] mode,
	 input in_candidate_1,
	 input in_candidate_2,
	 input in_candidate_3,
	 output [7:0] count_candidate_1,
	 output [7:0] count_candidate_2,
	 output [7:0] count_candidate_3,
	 output candidate_1,
	 output candidate_2,
	 output candidate_3);

Waveform