GitHub - ubyhzargam/FIFO: I have modelled a FIFO memory with depth of 16. The circuit is described using verilog language. I have also synthesized the design using an open source tool named Yosys, for performing technology mapping I have used a 45 nm pdk of a typical process- The library used NLDM modelling. I also performed logic optimization using Yosys using commands.

The above is the code for FIFO of depth 16.

Now , let us perform logic senthesis on this RTL code.
There are several steps in logic synthesis -

RTL Synthesis : Converts RTL (verilog) code to Generic Netlist. This is further subdivided into Parsing + Elaboration + Translation and optimization
Logic Optimization : Peforms logic Optimization on Generic Netlist to get Optimized netlist of generic gates.
Technology mapping : The generic netlist is mapped to standard cells through a Process design kit(PDK) which contains information about standard cells
Technology dependendent logic Optimization : We get optimized netlist mapped to a particular technology.

This is the Internal model representation of Verilog code i.e. Syntax tree
This is performed using the commands -
read_verilog top.v
show

This is the generic gate netlist

This is the optimized generic gate netlist

This is technology mapped netlist done using yosys and 45 nm cmos pdk.

This is the optimized technology mapped netlist

Using stat -liberty command we can also get or estimate the area of the chip -

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
README.md		README.md
depth16fifo.v		depth16fifo.v
synth.dot		synth.dot

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