VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls
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Dec 17, 2019 - VHDL
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altera-fpga
Here are 23 public repositories matching this topic...
FPGA implementation of the popular logic game using VHDL and Altera DE1
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Apr 21, 2018 - VHDL
An 8-bit processor in VHDL based on a simple instruction set
processor-architecture fpga processor vhdl verilog vivado hardware-designs hdl xilinx-fpga processor-simulator hardware-description-language digital-electronics altera-fpga processor-design
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Mar 7, 2019 - VHDL
FPGA and CPLD programming, tutorials and information I figure out.
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Feb 20, 2022 - VHDL
Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.
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Nov 14, 2020 - VHDL
Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.
fpga robo altera vhd l298n l298 altera-fpga l298n-h-bridge engenharia-de-computacao insper de0 de0cv de0-cv robot-fpga robo-fpga
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Nov 1, 2019 - VHDL
A simple sram controller and test for the altera DE1 FPGA board
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Apr 2, 2019 - VHDL
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
fsm vhdl intel finite-state-machine quartus-prime vga-driver vga-controller altera-fpga vhdl-coursework quartus2 altera-de1
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Feb 7, 2023 - VHDL
Hardware Praktikum at Uni Freiburg
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Nov 8, 2018 - VHDL
Digital clock in VHDL, on Altera Cyclone IV FPGA Board A-C4E6. This work was presented on PLP discipline during electrical engineer course at Mackenzie Presbyterian University.
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Nov 23, 2019 - VHDL
Pong VGA for a DE0 Altera model FPGA programmed in VHDL.
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May 28, 2021 - VHDL
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Dec 8, 2017 - VHDL
Objetivo do Projeto Implementação de circuitos digitais em FPGA. Exemplos de lógica combinacional, sequencial e sistemas embarcados. Testes práticos com periféricos (LEDs, botões, displays, etc.).
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Jul 11, 2025 - VHDL
Lab exercises on digital circuit design using Altera Quartus 9.1sp2
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Jan 31, 2022 - VHDL
The work presented is designed to simulate the operation of an automatic coffee machine. It will manage the machine operation by exploiting the processing capabilities of the FPGA.
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Dec 16, 2019 - VHDL
Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board
vhdl altera seven-segment vhdl-modules seven-segments-display altera-fpga vhdl-coursework seven-segment-display altera-de1 terasic-de1
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Apr 12, 2019 - VHDL
Team 21 - Mini-Project
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Jul 30, 2024 - VHDL
A scalable and freely configurable function generator in VHDL
open-source fpga vr vhdl virtual-reality open-science hci human-computer-interaction function-generator actuator-control tactile-feedback altera-fpga papers-with-code tactile-perception
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Nov 20, 2022 - VHDL
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