quartus-prime

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Install Intel FPGA 'Quartus Prime' software on remote servers

SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

Trying to get a new skill

Tutorial de instalação do Quartus Prime no Linux

Custom Altera FPGA designs by Olaoluwa Raji. This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA using VHDL.

Full tutorial about how to install Quartus Prime software in different systems

A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)

A script to convert the Intel Quartus IDE to dark mode using QDarkStyleSheet with some modifications.

This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.

This repository showcases the projects I developed for the DE10-Lite board as part of the "FPGA Capstone: Building FPGA Projects" course on Coursera.

Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs

FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1

An 8-bit RISC based processor designed in verilog with x86 instructions.

Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

A Python-based IP Core Management Infrastructure.

Collection of scripts for EDA tools

FPGA-based Sony SIRC infrared receiver and pulse-width decoder in VHDL for the Terasic DE1-SoC, featuring an FSM, LED output and testbench.

This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book.