altera-quartus

Here are 16 public repositories matching this topic...

Multimedia-Processing / Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。

Updated Oct 25, 2023
Verilog

EngineerMichael / ModelSim-Altera-Project-Electronics-

⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.

modelsim vhdl-code altera-fpga altera-de1 altera-quartus synchronous-counter

Updated Feb 24, 2025

ariel-wolfe / MIPS-32-Bit-Single-Cycle-Processor

Star

Creating a 32-bit single cycle processor using VHDL on Altera Quartus and MIPS assembly commands. Each component was created and emulated using VHDL code. After creating block symbols of each component, the entire processor was connected and compiled for functionality.

vhdl mips-assembly single-cycle-processor altera-quartus

Updated Feb 22, 2023

jpenolio75 / tron_on_vga

Star

An implementation of the popular Tron arcade game on the Altera DE2-115 board for UNLV CpE 302 Synthesis and Verification Using Programmable Devices final.

systemverilog vga tron-game de2-115 nintendo-entertainment-system altera-quartus

Updated May 10, 2023
SystemVerilog

jpenolio75 / smp8

Star

An implementation of a simple 8-bit microprocessor on an Altera DE2-115 board for UNLV CpE 300L Digital Systems Architecture and Design final project.

verilog microprocessor de2-115 altera-quartus

Updated May 10, 2023
Verilog

yavuzCodiin / 4-Bit_Calculator

Star

4-bit calculator with all operations we set up for calculator. It have some main parts which are FSM(Finite State Machine) which has MOP(Micro-operations). Datapath that includes calculator's brain which is ALU(Arithmetic Logic Unit), multiplexers and hexadecimal decoder.

fsm register vhdl lrs alu multiplexer ars fpga-programming de0-board lls altera-quartus cyclone-iii

Updated Oct 22, 2023
VHDL

mit41301 / Z80_CYCLONE_IV_EP4CE6E22C8

Star

Simple Z80 CPU with inbuilt 8kB ROM and 4kB RAM using T80 core. Operating at 50MHz clock with Tx, Rx and reset. UART terminal at 115200 baud. One 8 bit output port at 145 connected to LEDs.

vhdl z80 verilog systemverilog modelsim zilog softcore altera-fpga altera-quartus t80

Updated Aug 15, 2025
BASIC

GeoKrom / UoI-Digital-Design-II-course

Star

Lab exercises on digital circuit design using Altera Quartus 9.1sp2

fpga vhdl digital-circuits digital-design altera-fpga altera-quartus altera-cyclone-ii

Updated Jan 31, 2022
VHDL

fyemane / Bidirectional-visitor-counter

Star

A bidirectional room visitor counter using schematic capture and AHDL on Intel Quartus Prime using an Altera CPLD

intel cpld falstad altera-quartus

Updated Sep 19, 2022
HTML

SKpro-glitch / Multi-Bit-Comparator

Star

Variations of a multi-bit generalized magnitude comparator for different area and timing.

serialization fpga rtl vlsi comparator verilog-hdl logic-circuit serial-port digital-design low-power xilinx-vivado power-gating fpga-programming vlsi-design rtl-design altera-quartus register-transfer-level

Updated Jun 26, 2025
D

Charlie-Ramirez-Animation-Studios-de-MX / VHDL-Basicos

Star

Programas Basicos en Lenguaje VHDL de Diseño Logico y Diseño de Circuitos Digitales para Uso y simulacion con QuartusII y los FPGA Cyclone III de Altera (Compilados y compatibles con la FPGA EP3C16F484C6N) Para Practica en la Licenciatura de Ingenieria Electrica Electronica e Ingenieria en Computación Bajo Licencia MIT

fpga vhdl altera unam quartus vhdl-examples quartus2 altera-quartus

Updated Jun 3, 2024
VHDL

mcleber / Bug_fixes_and_Configuration_Files

Star

This repository compiles notes, fixes, and configuration files related to bugs and issues encountered during the installation and use of various software tools on both Linux and Windows platforms.