Simple Z80 CPU with inbuilt 8kB ROM and 4kB RAM using T80 core. Operating at 50MHz clock with Tx, Rx and reset. UART terminal at 115200 baud. One 8 bit output port at 145 connected to LEDs.
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Aug 15, 2025 - BASIC
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altera-fpga
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Highspeed BASIC-52 V1.31 + I2C softcore running from internal 12kB ROM and 4kB RAM implemented inside MAX10 FPGA.
microcontroller fpga vhdl verilog systemverilog modelsim highspeed softcore i2c-master max10 altera-fpga max1000 quartus-18-1 basic-52 8bit-computers mcs51-8051
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Jul 12, 2025 - BASIC
80C52 + 12kB ROM + 16kB RAM on Altera CYCLONE IV EP4CE6 running with BASIC-52 +I2C on 12kB ROM
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Aug 8, 2025 - BASIC
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