terasic-de0

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An attempt at a small Verilog implementation of the original Apple 1 on an FPGA

apple verilog retrocomputing ice40 icoboard apple1 terasic-de0 ice40hx8k upduino tinyfpga

Altera Quartus project for Altera Cyclone III FPGA boards which uses one manager board and two worker boards to sort an array of numbers in parallel.

vhdl altera altera-fpga terasic-de0 cyclone-iii

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