VeeR EH1 core

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

32-bit 5-stage pipelined RISC-V processor in SystemVerilog

A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL

MIPS CPU in verilog

A tiny 8 bit RISC ISA for on-chip/on-FPGA management purposes

Research project for creating pipeline CPU without hazards running kernel-less OS

It's a simple verilog based MIPS microarchitecture hardware design.

4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.

Implements a RISC processor that executes a set of ARMv7 instructions.

Made a fully functional CPU model capable of performing essential computing tasks, such as executing instructions from memory, handling data with load and store operations.

A SystemVerilog implementation of a single-cycle RISC-V processor supporting RV32I ISA. Features modular design with instruction fetch, decode, ALU, and memory stages. Ideal for FPGA prototyping, computer architecture studies, and educational projects. Synthesizable codebase for hobbyists and developers exploring processor design.

Computer Architecture final project